Tang Console 138K
- Programación del FPGA con Verilog.
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Código Blink Led
//Qdynamic Led Blink TC138K
module blink (input i_clk, output o_led);
reg [31:0] counter = 0; // always initialize registers
assign o_led = counter[24]; // output is bit 24
always @(posedge i_clk)
counter <= counter + 1;
endmodule